The present invention relates generally to digital logic circuit devices and, more particularly, to a design structure for implementing speculative clock gating of digital logic circuits.
Clock gating is a widely adopted technique for deactivating particular resources within an integrated circuit (IC). A clock gating circuit activates/deactivates an IC resource by gating a clock signal provided to the resource. In response to an active clock enable signal, the clock gating circuit passes the clock signal to a target resource. Conversely, the clock gating circuit inhibits or blocks the clock signal from reaching the target resource when the clock enable signal is inactive. Thereby, the states of individual storage devices (e.g., flip-flops) associated with the target resource do not needlessly change state, as would otherwise be the case if the clock signal were always passed through to the resource.
In particular, fine-grained clock gating is an important technique for reducing the power consumption of digital logic circuits in pipelined designs where information developed in earlier stages of the pipeline may be used to create clock gating signals for use in later pipeline stages. However, in some cases, the communication and logic delays incurred in developing a precise clock gating signal (i.e., a signal which never fails to gate any clock pulse that could have been gated) may be so large that the signal actually arrives too late to gate the clock, rendering the gating signal infeasible.
Accordingly, it would be desirable to be able to address the delays associated with traditional precise clock gating, but in a manner that still offers advantages in terms of power savings with respect to circuits that are not clock gated to begin with.